对NMOS(N-metal oxide semiconductor)管交叉耦合逻辑(NMOS-transistor cross coupling logic,NCCL)的能量回收电路进行了研究,PMOS(P-metal oxide semiconductor)管作为输入管来降低纳米CMOS工艺中栅氧化层上的漏电流以减小功耗;在此基础上实现了绝热JK触发器电路.在90 nm CMOS BSIM3工艺模型下,用HSPICE对NCCL反相器及其JK触发器进行了模拟分析,结果表明NCCL反相器的工作频率可达到1 GHz;与ECRL(efficient charge recovery logic)反相器相比,当负载电容、时钟频率和电源电压中某一参数变化时,NCCL的功耗都出现不同程度的降低;在相同的工作条件下NCCL JK触发器的功耗约为ECRL 的50%.
The energy recovery circuit based on NMOS(N-Metal Oxide Semiconductor)-transistor cross coupling logic(NCCL)is studied.PMOS(P-Metal Oxide Semiconductor)transistors are used as the input tube to reduce the leakage current on the oxide gate layer in nanometer CMOS process.NCCL JK flip-flop is constructed by these techniques.The circuits are simulated by HSPICE in 90 nm CMOS BSIM3 process,and the simulation results show that NCCL inventor’s operation frequency can reach to 1 GHz. Compared with the ECRL(Efficient Charge Recovery Logic)inventor,when load capacity or clock frequency or power supply changes,the power consumptions of NCCL inventor decline to different degrees.In the same operate condition,the power consumption of NCCL JK flip-flop is about 50% of the ECRL JK flip-flop.
[1] MARKOVIC D,WANG C C,ALARCON L P,et al.Ultralow-power design in near-threshold region [J].Proceedings of the IEEE,2010,98(2):237-252.DOI:10.1109/JPROC.2009.2035453.
[2] PAUL B C,AGARWAL A,ROY K.Low-power design techniques for scaled technologies [J].Integration,the VLSI Journal,2006,39(2):64-89.DOI:10.1016/j.vlsi.2005.12.001.
[3] MOON Y,JEONG D K.An efficient charge recovery logic circuit[J].IEEE Journal of Solid-state Circuits,1996,31(4):514-522.
[4] 郭宝增,张亚朋.基于改进型ECRL电路的触发器设计[J].微型机与应用,2010(2):23-26. GUO Baozeng,ZHANG Yapeng.Improved ECRL-based flip-flop design[J].Microcomputer & Its Applications,2010(2):23-26.
[5] 张丽,郭宝增.基于ECRL电路的两种改进绝热电路[J].微型机与应用,2011,30(16):19-21. ZHANG Li,GUO Baozeng.Two improved adiabatic circuits based on ECRL[J].Microcomputer & Its Applications,2011,30(16):19-21.
[6] SHI J Y,LI H Y,XU Y B.Design of the approved low power energy recovery logic circuit[J].Advanced Materials Research,2013,662:851-855.DOI:10.4028/www.scientific.net/AMR.662.851.
[7] YEO Y C,LU Qiang.Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric[J].IEEE Electron Device Letters,2000,21(11):540-542.DOI:10.1109/55.877204.
[8] HU Jianping,LIU Binbin.Designs of 2P-2P 2N energy recovery logic circuits [J].Research Journal of Applied Sciences,Engineering and Technology,2013,5(21):4977-4982.
[9] Nanoscale Integration and Modeling Gralp at ASU Predictive Technology Model(PTM)[S/OL].(2001-5-31)[2014-6-20].http://www.ptm.asu.edu.
[10] INUKAI T,TAKAMIYA M,NOSE K,et al.Boosted gate MOS(BGMOS):leakage-free circuits by device/circuit cooperation scheme[J].Integrated Circuits and Devices,2000,100(270):1-8.
[11] GHANI T,MISTRY K,PACKAN S,et al.Scaling challenges and device design requirements for high performance sub-50nm gate length planar CMOS transistors[Z].Symposium on VLSI Technology,Hawaii:2000.
