Journal of Hebei University(Natural Science Edition) >

2014 , Vol. 34 >Issue 1: 89 - 93

DOI: https://doi.org/10.3969/j.issn.1000-1565.2014.01.017

Design and implementation of deep sub-micron parallel CRC32 coding chip

  • GUO Baozeng ,
  • WU Pengfei
Expand

Online published: 2014-01-25

Fold

Cite this article

GUO Baozeng , WU Pengfei . Design and implementation of deep sub-micron parallel CRC32 coding chip[J]. Journal of Hebei University(Natural Science Edition), 2014 , 34(1) : 89 -93 . DOI: 10.3969/j.issn.1000-1565.2014.01.017

References

[1] 张树刚, 张遂南, 黄士坦, ZHANG Shu-gang, ZHANG Sui-nan, HUANG Shi-tan. CRC校验码并行计算的FPGA实现 [J]. 计算机技术与发展 2007.doi:10.3969/j.issn.1673-629X.2007.02.016
[2] 樊昌信, 张甫翊, 徐炳祥. 通信原理 [M]. {H}北京:国防工业出版社 2001.
[3] MING-DER SHIEH, MING-HWA SHEU, CHUNG-HO CHEN. A Systematic Approach for Parallel CRC Computations [J]. Journal of information science and engineering: JISE 2001, 3(3).
[4] Ramabadran T.V., Gaitonde S.S.. A tutorial on CRC computations [J]. IEEE Micro 1988, 4(4).
[5] 夏宇闻. Verilog数字系统设计教程 [M]. {H}北京:北京航空航天大学出版社 2003.
[6] 韩雁, 洪慧, 马绍宇. 集成电路设计制造中EDA工具实用教程 [M]. {H}杭州:浙江大学出版社 2007.
Options
Outlines

/

〈 〉