Abstract: The energy recovery circuit based on NMOS(N-Metal Oxide Semiconductor)-transistor cross coupling logic(NCCL)is studied.PMOS(P-Metal Oxide Semiconductor)transistors are used as the input tube to reduce the leakage current on the oxide gate layer in nanometer CMOS process.NCCL JK flip-flop is constructed by these techniques.The circuits are simulated by HSPICE in 90 nm CMOS BSIM3 process,and the simulation results show that NCCL inventor’s operation frequency can reach to 1 GHz. Compared with the ECRL(Efficient Charge Recovery Logic)inventor,when load capacity or clock frequency or power supply changes,the power consumptions of NCCL inventor decline to different degrees.In the same operate condition,the power consumption of NCCL JK flip-flop is about 50% of the ECRL JK flip-flop.

Key words: NMOS transistor cross coupling, NCCL, NCCL JK flip-flop, low power consumption