Journal of Hebei University(Natural Science Edition) >

2006 , Vol. 26 >Issue 3: 310 - 314

DOI: https://doi.org/10.3969/j.issn.1000-1565.2006.03.021

A Design Scheme of 2-digitization 4DPSK Demodulator Based on CPLD

  • WANG Lan-xun ,
  • ZHANG Qing-shun ,
  • HUANG Ya-li ,
  • SONG Tie-rui
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Online published: 2006-05-25

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WANG Lan-xun , ZHANG Qing-shun , HUANG Ya-li , SONG Tie-rui . A Design Scheme of 2-digitization 4DPSK Demodulator Based on CPLD[J]. Journal of Hebei University(Natural Science Edition), 2006 , 26(3) : 310 -314 . DOI: 10.3969/j.issn.1000-1565.2006.03.021

References

[1] 王兰勋, 潘立冬, 郑晓昆. 一种用CPLD实现的2DPSK调制解调器 [J]. 河北大学学报（自然科学版） 2004.doi:10.3969/j.issn.1000-1565.2004.05.019
[2] 王兰勋, 荣民. 一种位同步时钟提取方案及实现 [J]. 无线电工程 2003.doi:10.3969/j.issn.1003-3106.2003.10.021
[3] 樊昌信, 张甫翊, 徐丙祥. 通信原理 [M]. 北京:国防工业出版社 2001.
[4] 卢毅, 赖杰. VHDL与数字电路设计 [M]. 北京:科学出版社 2001.
[5] HOGENAUER B. An economical class of digital filters for decimation and interpolation [J]. IEEE Transactions on Acoustics Speech and Signal Processing 1981, 29(02).
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